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Renesas Electronics /R7FA6M3AH /GLCDC /GR1_VEN

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Interpret as GR1_VEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PVEN

PVEN=0

Description

Graphics 1 Register Update Control Register

Fields

PVEN

Control of graphics n module register value reflection to internal operations.Reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS).

0 (0): Disables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS).

1 (1): Enables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS).

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data